The present invention relates to a peak detection circuit used in a device such as an Auto Gain Controlled Amplifier which detects a peak value of a predetermined signal.
FIG. 4 shows a peak detection circuit 101 according to a prior art. The peak detection circuit 101 includes a differential amplifier circuit comprising transistors Q1, Q2, resistive elements RL1, RL2, a first constant-current source CCS1, and an emitter-follower circuit comprising transistors Q3, Q4 connected each other in the way of darlington connection. The peak detection circuit 101 also includes a pad PAD, a capacitive element CP and a second constant-current source CCS2.
One end of the resistive element RL1 and one end of the resistive element RL2 are commonly connected with a power source level VCC. The other end of the resistive element RL1 is connected with a collector of the transistor Q1, whereas the other end of the resistive element RL2 is connected with a collector of the transistor Q2 and a base of the transistor Q3. The transistor Q1 is controlled by an input signal In which is input to a base of the transistor Q1, and the transistor Q2 is controlled by a reference signal Ref which is input to a base of the transistor Q2. Emitters of the transistors Q1, Q2 are connected with a ground level GND through the first constant-current source CCS1 which generates constant-current Ie.
Collectors of the transistor Q3, Q4 are commonly connected with the power source level Vcc. An emitter of the transistor Q3 is connected with a base of the transistor Q4 and the pad PAD. The pad PAD is connected with one end of the capacitive element CP, and the other end of the capacitive element CP is connected with the ground level GND. An emitter of the transistor Q4 is connected with the ground level GND through the second constant-current source CCS2 which generates a constant-current If. Thus, an output signal Out of the peak detection circuit 101 is output from the emitter of the transistor Q4.
In the following, the operation of the peak detection circuit 101 according to the prior art having the above-mentioned structure is described. The input signal In input to the base of the transistor Q1 is differentially amplified based on the reference signal Ref input to the base of the transistor Q2. The differentially amplified signal (referred as an amplifier signal Sa) is input to the base of the transistor Q3. At this step, if the voltage of the amplifier signal Sa is larger than the sum of the voltage of the capacitive element CP and the voltage between the base and the emitter (about 0.8 V) of the transistor Q3, the transistor Q3 is turned on. With such operation of the transistor Q3, a signal of "H" level is input to the base of the transistor Q4, the emitter of which outputs the output signal OUT based on the constant-current If generated from the second constant-current source CCS2. In short, the peak detection circuit 101 according to the prior art detects a peak voltage value of the input signal In by means of the reference signal Ref. A peak voltage value of the input signal In can be adjusted with ease by changing the voltage of the reference signal Ref.
After the transistor Q3 is turned off, the transistor Q4 remain in the on state for a predetermined period depending on time spent for discharge of the capacitive element CP which has been charged by an emitter current of the transistor Q3. The period of the transistor Q4 being kept in the on state is usually adjusted depending on the frequency of the input signal In. For example, in the case that the frequency of the input signal In is about 1 GHz, a capacitive element CP of some pFs is used in accordance with the frequency of the input signal. On the contrary, in the case that the frequency of the input signal In is about 100 GHz, a capacitive element CP of several hundreds pFs is required. When the peak detection circuit 101 is formed as a semiconductor integrated circuit, a chip capacitor (not shown) provided at the exterior of the circuit is connected with the pad PAD so as to match the frequency of the input signal In, because it is difficult to provide a capacitive element CP with a large capacitance of several hundreds pFs in the circuit.
However, in the peak detection circuit 101 according to the prior art, in the case that the chip capacitor connected with the capacitive element CP and pad PAD, is not charged enough, for example, immediately after rise of the power source voltage, when the input signal In is input and the transistor Q3 is turned on, an excessive amount of current flows into the transistor Q3. This causes deterioration of the transistor Q3. The same problem is caused when the pad PAD is contacted with the ground level GND for some reason, or when inappropriate voltage had been input to the pad PAD at the experimental operation of the peak detection circuit 101.